COMON - The Compact Modelling Network - is a consortium of 15 universities and companies, which came together in an attempt to transfer the scientific and technological knowledge from academia to industry, to strengthen the European integrated circuit (IC) industry with powerful design automation methodologies and to achieve integration of European research in a fragmented area for the benefit of both young and experienced researchers.
The coordinator of this team is Prof. Benjamin Iniguez, from University Rovira i Virgili.
The global structure of the project is divided into Working Groups (WGs) - each one of the addressing one type of devices. The devices addressed are devices coming from technologies of interest to European industry, and in which there is a strong compact modeling work in Europe - and Work Packages (WPs) - each one focusing on one activity related to all the common tasks.
Working Groups
WG1: Multiple-Gate SOI MOSFETs
Partners: UCL, URV, UniK, EPFL, ULP, TUC, ITE, Infineon, AdMOS, AIM-Software.
WG2: High Voltage MOSFETs
Partners: AMS, EPFL, TUC, AdMOS, Dolphin, Melexis, AIM-Software.
WG3: Advanced III-V HEMTs
Partners: TU-Ilmenau, UniK, URV, RFDM (UK), AIM-Software
Working Packages
WP1: Compact modelling development and parameter extraction
Objectives: Complete compact models of the target devices will be developed using as a basis the modelling techniques the partners previously developed. The compact modelling activity will include the
development of models for the thermal effects, the RF and microwave behaviour, the low and high
frequency noise, the harmonic distortion and the parameter fluctuations (in terms of the process
parameters). Statistical modelling will be carried out for the modelling of process parameter
variations. Model parameter dependences on process parameters will be determined. Geometry and
temperature dependences of the model parameters will be included.
WP2: Compact modelling implementation and benchmarking
Objectives: The compact models will be implemented in circuit simulators. The models will be written in VHDL-AMS and Verilog-A. VHDL-AMS to C and Verilog-A to C compilers tools will be used to
perform compact model implementation into circuit simulators. The model codes will be optimized
and standardized. The model implementation will also be carried out at higher levels of abstraction,
using VHDL-AMS and Verilog-A. The compact models, once implemented in EDA tools, will be evaluated for circuit design
purposes. COMON will perform analysis of convergence, CPU time, statistic circuit simulation...
Conventional SPICE-like and RF simulators will be used. All analysis (DC, AC, transient, noise,
RF, harmonic distortion) will be considered.
WP3: Evaluation and demonstration of design tools on test chips
Objectives: We will carry out a comprehensive evaluation of the compact models by simulating a number of circuit designs (of different types: analog, digital, RF) , for the different targeted technologies. We
will perform analyses of convergence, CPU time, statistic circuit simulation, etc, for different types
of analyses: DC, AC, transient, noise, RF, harmonic distortion. Several types of simulators (in
which the models will be implemented) will be used for the evaluation.
Finally, we will demonstrate the effectiveness of the compact models implemented in the design
tools by means of using them for the design of test chips, to be fabricated by the industrial partners.
The test chips will contain different types of circuits: digital, analog and RF. The experimental
performances of the test chips will be compared with the ones predicted by the compact models.
WP4: Dissemination, training, exploitation and IPR management
Objectives: The dissemination of results will be performed through scientific publications in international journals, presentations in conferences, and maintenance of a web site. A special Workshop on
Compact Modelling (MOS-AK) will be organized twice a year. Training courses and summer
schools will be organized. Regarding exploitation, each partner will compile detailed exploitation
plans, which will be updated periodically. The completion of the compact models, and their
implementation in design tools, as well as the dissemination of the results, will create many
exploitation opportunities. Finally, Intellectual Property Rights (IPR) management concerns with
the establishment of proper policies and guidelines for intellectual property protection internally and
externally to the Consortium.
WP5: Project management
Objectives: The management structure we consider is not complicated, but effective. URV is in
charge of the overall and administrative project management.
|
