Activities shall include , but will not be limited to, the following tasks:
- Improvement, optimization, benchmarking and standardization of models implemented in circuit simulators, previously developed by the participants in the framework of European or national funded projects.
- Optimization and standardization of parameter extraction techniques. Study of process fluctuation effect on the electrical performance captured by compact models. Correlation of fitting model parameters to process variables.
- Model generation from 2/3D numerical and EM simulation. Determination of compact model parameters from the device structure data (computationally cheaper than from numerically calculated characteristics).
- Model evaluation for technology predictions.
- Compact model evaluation for circuit design: convergence, CPU time, statistic circuit simulation...Conventional SPICE-like and HF simulators will be used. All analysis (DC, AC, transient, noise, RF, harmonic distortion) will have to be used.
- Behavioral modeling (i.e. Verilog-A, VHDL-A). Implementation and validation of compact models in Hardware Description Languages.
- Electronic Design Automation activities (Verilog-A to C compilers): open-source tools which perform compact model implementation from HDLs into circuit simulators. Application of those tools to different compact models.
- New simulation techniques (for example, solutions for the frequency domain, thermodynamic effects, optical effects...).
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