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Full Name: 2nd Announcement and Call for Papers EUROSOI 2010 - 6th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits Location: Grenoble, France Venue: MINATEC, 3 parvis Louis Neel, Grenoble Date: Jan 25, 2010 - Jan 27, 2010 Description: 1. Synthesis of advanced SOI wafers: Ge, SiGe and strained layers, SOI heterostructures, alternative semiconductors. 2. Materials evaluation, properties of ultra-thin films and buried oxides, defects and stress, interface quality. 3. SOI MOSFETs: characterization, modeling and simulation of advance mechanisms, parameter extraction, variability, low and high-temperature behavior, radiation effects, reliability issues. 4. Circuit design, process and applications: low power/voltage and RF circuits, innovative memories, high voltage devices, imagers, sensors, photovoltaics and MEMS. 5. More than Moore perspectives: multiple-gates, 3D stacks of devices and circuits, nanowires, NEMS, tunneling transistors, heterogeneous integration etc. Other details:
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