Full Name: MOS-AK Rome 2010: over 20 Years of Enabling Compact Modeling R&D Exchange
Location: Rome, Italy
Venue: The Faculty of Engineering, Sapienza Università di Roma, Via Eudossiana 18
Date: Apr 8, 2010 - Apr 9, 2010
Description:
1. HiTech forum to discuss the frontiers of the compact/spice modeling and its Verilog-A standardization.
2. MOS-AK/GSA Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors.
3. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.
Topics:
1. Compact model development
2. Implementation
3. Deployment
4. Standardization
5. Frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulation.
Other details:
Important dates:
1. 1st Announcement - Dec. 2009
2. 2nd Announcement - Jan. 2010
3. Final Workshop Program - Feb.2010
4. MOS-AK/GSA Workshop - Apr 8-9, 2010
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