The Compact Modelling Project

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Objectives
The goal of our project is to address the full development chain of Compact Modelling (CM) of advanced CMOS and III-V technologies, from the technology level to the system level. Analytical, compact models, which balance accuracy and computational complexity, are the type of device models needed for circuit simulation tools. Compact modelling is the only feasible path for a practical implementation of a generalized IC design flow. COMON will target the semiconductor devices that are currently considered as "state-of-the-art" and are the most promising for capturing future digital, analog and high frequency communication IC markets: Multi-Gate MOSFETs, high voltage MOSFETs (especially LD MOSFETs) and advanced HEMTs. During the last years, a number European teams have become pioneers in the development of compact models in such advanced devices; although these models are still not complete, they can be used as kernel models for the development of more complete models which will incorporate all geometry effects, temperature dependences, thermal effects low and high frequency noise, and high frequency behaviour. Recently developed new techniques will be applied to make the models based on 2D or 3D electrostatic analysis, thus reducing the number of model parameters and avoiding the use of empirical parameters. The extension of the models to the RF regime will be crucial, since the target devices are especially promising in the high frequency operation. It should be remarked that, many important RF figures of merit have not gained much attention from the ponit of view of modelling. The mission of COMON is to complete the compact models for the target devices, and also to make them suitable for the industrial circuit design; for that purpose, the other steps of the full compact modeling chain should be performed. COMON will carry out the implementation and incorporation in circuit simulators of the models previously developed by the participants, and also will be in charge of their improvement, optimization, benchmarking and standardization. Particular emphasis will be put in the use of VHDL-AMS and Verilog-A as a standard language for modelling implementation. The use of Verilog-A has been proposed as a new model development methodology that increases the synergy of the different phases of the compact modelling chain, increasing the degree of standardization of compact models. Once the compact models are implemented, COMON will perform the compact model evaluation for analog, digital and RF circuit design: convergence, CPU time, statistic circuit simulation... Another important task to be done is the optimization and standardization of parameter extraction techniques. The resulting algorithms will be optimized and incorporated to EDA tools. On the other hand, , the models will take into account fluctuations of process parameters, which become more significant as devices are scaled down. The model parameters will be correlated to process parameters, therefore being able to analyze and predict the effect of the statistical variations of the process parameters. Finally, the validity of the compact models implemented in the design tools will be demonstrated by means of applying them to design a number test chips, to be fabricated by the industrial partners. The experimental performances of the test chips will be compared with the ones predicted by the compact models. In our consortium, the three participating foundries will be responsible for the manufacturing of test chips for the compact model development and evaluation. The academic teams have a large experience in compact modeling of different types of devices and will have the main responsibility of model development in the project. The evaluation of the compact models will be performed by the teams who implemented them in EDA tools together with partners specialized in circuit design (universities and companies), who will design the test circuits to validate the models. Therefore, the Consortium will be a communication platform for foundries, software vendors, circuit designers and universities regarding CM issues. COMON will establish a joint programme that will enable research through intersectorial and multidisciplinary collaboration, including researcher exchanges between academia and industry, as well as training activities. The industrial partners will be able to take advantage of the new compact models during the course of the project and start applying the new tools for production shortly after the end of the project. The incorporation of the new compact models in the design kits of modern semiconductor foundry partners will lead to faster and cost effective IC development cycles and higher integration levels.

Objectives

The goal of our project is to address the full development chain of Compact Modelling (CM) of advanced CMOS and III-V technologies, from the technology level to the system level. Analytical, compact models, which balance accuracy and computational complexity, are the type of device models needed for circuit simulation tools. Compact modelling is the only feasible path for a practical implementation of a generalized IC design flow.

COMON will target the semiconductor devices that are currently considered as "state-of-the-art" and are the most promising for capturing future digital, analog and high frequency communication IC markets: Multi-Gate MOSFETs, high voltage MOSFETs (especially LD MOSFETs) and advanced HEMTs. During the last years, a number European teams have become pioneers in the development of compact models in such advanced devices; although these models are still not complete, they can be used as kernel models for the development of more complete models which will incorporate all geometry effects, temperature dependences, thermal effects low and high frequency noise, and high frequency behaviour. Recently developed new techniques will be applied to make the models based on 2D or 3D electrostatic analysis, thus reducing the number of model parameters and avoiding the use of empirical parameters. The extension of the models to the RF regime will be crucial, since the target devices are especially promising in the high frequency operation. It should be remarked that, many important RF figures of merit have not gained much attention from the ponit of view of modelling. The mission of COMON is to complete the compact models for the target devices, and also to make them suitable for the industrial circuit design; for that purpose, the other steps of the full compact modeling chain should be performed. COMON will carry out the implementation and incorporation in circuit simulators of the models previously developed by the participants, and also will be in charge of their improvement, optimization, benchmarking and standardization. Particular emphasis will be put in the use of VHDL-AMS and Verilog-A as a standard language for modelling implementation. The use of Verilog-A has been proposed as a new model development methodology that increases the synergy of the different phases of the compact modelling chain, increasing the degree of standardization of compact models. Once the compact models are implemented, COMON will perform the compact model evaluation for analog, digital and RF circuit design: convergence, CPU time, statistic circuit simulation...

Another important task to be done is the optimization and standardization of parameter extraction techniques. The resulting algorithms will be optimized and incorporated to EDA tools. On the other hand, , the models will take into account fluctuations of process parameters, which become more significant as devices are scaled down. The model parameters will be correlated to process parameters, therefore being able to analyze and predict the effect of the statistical variations of the process parameters.

Finally, the validity of the compact models implemented in the design tools will be demonstrated by means of applying them to design a number test chips, to be fabricated by the industrial partners. The experimental performances of the test chips will be compared with the ones predicted by the compact models.

In our consortium, the three participating foundries will be responsible for the manufacturing of test chips for the compact model development and evaluation. The academic teams have a large experience in compact modeling of different types of devices and will have the main responsibility of model development in the project. The evaluation of the compact models will be performed by the teams who implemented them in EDA tools together with partners specialized in circuit design (universities and companies), who will design the test circuits to validate the models.

Therefore, the Consortium will be a communication platform for foundries, software vendors, circuit designers and universities regarding CM issues. COMON will establish a joint programme that will enable research through intersectorial and multidisciplinary collaboration, including researcher exchanges between academia and industry, as well as training activities. The industrial partners will be able to take advantage of the new compact models during the course of the project and start applying the new tools for production shortly after the end of the project. The incorporation of the new compact models in the design kits of modern semiconductor foundry partners will lead to faster and cost effective IC development cycles and higher integration levels.

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